CadenceLIVE China 2025

Track 1 - Custom Analog Design

08/19/2025 13:00 to
13:30

CA01_The Future Is Now: Technology Breakthroughs for the Virtuoso Studio and Spectre Simulation Platforms

Zhong Fan
Cadence

08/19/2025 13:30 to
13:50

CA02_Application of Virtuoso Schematic Migration in Analog Circuit Migration

Shengli Fang
Sanechips

08/19/2025 13:50 to
14:10

CA03_Method of Decreasing Memory Consuming and Improving Capability for Multi-Tone Simulation from Cadence Spectre RF

Yunpu Zhang
UNISOC

08/19/2025 14:10 to
14:30

CA04_Application of Spectre X GPU in Large-Scale Analog Circuit Simulation

Kaibin Zhang
Sanechips

08/19/2025 14:30 to
14:50

CA05_Virtuoso APR for Stdcell: The Most Anticipated Automatic Placement and Routing Flow

Yonggui Zhang
ESWIN

08/19/2025 14:50 to
15:10

CA06_Application of FMC SmartCorner Based on ML Algorithms in the Project

Xingbo Yang
Sanechips

08/19/2025 15:10 to
15:30

CA07_SRAM Simulation and Verification with Spectre FX Simulator

Shoudao Wu
UNISOC

08/19/2025 15:30 to
16:00

TEA BREAK

08/19/2025 16:00 to
16:20

CA08_Advanced Parasitic Analysis Solution to Speed Up Post - Simulation Convergence

Da Cheng
Amlogic

08/19/2025 16:20 to
16:40

CA09_Optimizing PLL Transient Simulation: An Efficient Measurement Method Based on PLLMeasure

Xiang Zhao
ASR

08/19/2025 16:40 to
17:00

CA10_Accelerating Simulation Verification for High-Precision Large-Scale Analog Design Circuit Using Spectre X-GPU Simulator Engine

Chaolin Zhang
UNISOC

08/19/2025 17:00 to
17:20

CA11_Application of S-Parameter Quality Checking and Fitting Tool in the High-Speed Circuit Simulation Flow

Bo Zhang
Sanechips

Track 2 - Digital Design and Signoff

08/19/2025 13:00 to
13:30

DD01_Digital Design Implementation Innovation Roadmap

Yufeng Luo
Cadence

08/19/2025 13:30 to
13:55

DD02_Early Power Planning and Rapid Implementation Flow Based on Cadence Innovus FlashPG

Guangzheng Xiao
Sanechips

08/19/2025 13:55 to
14:20

DD03_Application of Voltus Insight AI in Physical Implementation of High-Performance CPU Cores

Shu Jiang
Jaguarmicro

08/19/2025 14:20 to
14:45

DD04_Efficient Clock Tree Synthesis Method and Application Based on Innovus COD

Aolin Li
Sanechips

08/19/2025 14:45 to
15:10

DD05_Research on IR Drop Optimization for Advanced Process ASICs Based on the Voltus-Insight AI Flow

Zhen Liang
UNISOC

08/19/2025 15:10 to
15:35

DD06_Optimization Strategy of X-State Based IR Drop in Voltus

Shining Dong
NXP

08/19/2025 15:35 to
16:05

TEA BREAK

08/19/2025 16:05 to
16:35

DD07_Accelerating Product Design Leveraging Cadence Managed Service in the Cloud

Mahesh Turaga
Cadence

08/19/2025 16:35 to
17:00

DD08_Quick PBA Timing Evaluation and Optimization Methodology for Critical Deep Logic Paths

Glen Ge
NXP

08/19/2025 17:00 to
17:25

DD09_Signoff Application Based on Llitmus-Xcelium Static Timing Constraint File

Shuang Xue
Sanechips

Track 3 - AI for Digital Design

08/19/2025 13:00 to
13:30

AD01_Design for AI, AI for Design

Ben Gu
Cadence

08/19/2025 13:30 to
13:55

AD02_SoC PPA Improvement with Combined Optimization of Turbo3 and Cadence Cerebrus in Genus and Innovus

Bingqian Xu
NXP

08/19/2025 13:55 to
14:20

AD03_Application of Joules-Based FlashReplay and XReplay in Place-and-Route (PR) Implementation

Yuewu Yan
Sanechips

08/19/2025 14:20 to
14:45

AD04_IR Drop Auto-Fix Based on Voltus InsightAI

Xue Gong
VeriSilicon

08/19/2025 14:45 to
15:10

AD05_Generative-AI Technology for Block and SoC IR Closure: Root-Cause and Repair Strategies

Siki Yang
Analog Devices

08/19/2025 15:10 to
15:40

AD06_Accelerating the Realization of Physical AI Chiplets

Michael Posner
Cadence

08/19/2025 15:40 to
16:10

TEA BREAK

08/19/2025 16:10 to
16:40

AD07_Introducing Conformal-AI Studio – AI Acceleration for Logic Equivalence, Functional ECOs, and Low-Power Signoff

Wells Jong
Cadence

08/19/2025 16:40 to
17:05

AD08_Efficient Collaborative Design and Verification Methodology for Multi-Bit Flip-Flops (MBFF) Based on Cadence Innovus and Conformal Tools

Sheng Yang
Sanechips

08/19/2025 17:05 to
17:30

AD09_Tackling the Rise of SDC in AI Processors with Health and Performance Monitoring

Dragon Hsu
proteanTecs

Track 4 - System Analysis

08/19/2025 13:00 to
13:30

SA01_Accelerating Innovation: AI-Driven Advances in Sigrity, Clarity and Optimality

Jian Liu
Cadence

08/19/2025 13:30 to
14:00

SA02_Research on Distributed Power Network Noise Simulation Methodology Based on Cadence Software Platform

Jin Zhang
Sanechips

08/19/2025 14:00 to
14:30

SA03_How to Complete the Simulation and Design of 112Gbps Channel with Powerful "AI"

Gang Huang
EDADOC

08/19/2025 14:30 to
15:00

SA04_Differentiate with Cadence IP and SoC Design & Embedded Services

Bhaskar Kolla
Cadence

08/19/2025 15:00 to
15:30

SA05_Effective Optimization for Packaging Design of RF Modules by Optimality AI

Shiyun Zhou
UNISOC

08/19/2025 15:30 to
16:00

TEA BREAK

08/19/2025 16:00 to
16:30

SA06_Application of VRF for High-Speed Co-Design of PKG and On-chip Passive Device and Trace

Haowei Lu
Sanechips

08/19/2025 16:30 to
17:00

SA07_Simulation Methods and Optimization Design of LPDDR5

Fanpeng Cao
NIO

08/19/2025 17:00 to
17:30

SA08_Channel Performance Optimization of UCIe Based on Clarity Routing Model Generation Scripts

Erling Pan
Sanechips

Track 5 - System Design and Thermal Solution

08/19/2025 13:00 to
13:30

SD01_System-Level Design, Powered by AI

Saugat Sen
Cadence

08/19/2025 13:30 to
14:00

SD02_Cadence IP Overview – Accelerate AI Innovation with Cadence Silicon Solution

Arno Li & Wei Wang
Cadence

08/19/2025 14:00 to
14:30

SD03_Cadence - Windchill Component Data Exchange

Jackie Yan
Schneider Electric

08/19/2025 14:30 to
15:00

SD04_PCB and Busbar E/T Co-Simulation

Dan Wu
H3C

08/19/2025 15:00 to
15:30

SD05_3D PCB Connection Check Based on OrbitIO

Xin Li
HONOR

08/19/2025 15:30 to
16:00

TEA BREAK

08/19/2025 16:00 to
16:30

SD06_Accelerating Aerodynamics: GPU-Powered CFD Simulation Workflow

Zhouqiao Zhao
BETA

08/19/2025 16:30 to
17:00

SD07_Designing and Simulating Next-Generation Data Centers and AI Factories with Cadence and NVIDIA

Scott Fu
NVIDIA

08/19/2025 17:00 to
17:20

SD08_Automatic Simulation Tool to Accelerate PCB Interconnection Verification

Xiangcheng Li
UNISOC

Track 6 - System Verification Solution and Methodology

08/19/2025 13:00 to
13:30

VE01_Broadening the Adoption of Hardware Emulation with Next-Generation Emulation Appliance

Michael Young
Cadence

08/19/2025 13:30 to
14:00

VE02_EMU Full-Scenario AVIP Rapid Iteration Verification Solution for XR Chip

Jin Yuan
GravityXR

08/19/2025 14:00 to
14:30

VE03_Power Analysis of AI Chip with Palladium DPA

Kai Xing
KUNLUNXIN

08/19/2025 14:30 to
15:00

VE04_Research on Accelerating Chiplet System-Level Verification with Distributed Simulation Technology

Jiashan Xu
Sanechips

08/19/2025 15:00 to
15:30

VE05_AP Chip Performance Verification Based on Palladium Platform

Yuxuan Zhen
Xiaomi

08/19/2025 15:30 to
16:00

TEA BREAK

08/19/2025 16:00 to
16:30

VE06_Optimization Techniques for Accelerating Gate-Level Simulation Using Xcelium: A NOACG and Fine-Grained Access Control Approach

Yang Lin
UNISOC

08/19/2025 16:30 to
17:00

VE07_Metrics-Driven Verification Solution Based on vManager

Jiangheng Pei
UNISOC

08/19/2025 17:00 to
17:30

VE08_Optimization of Coverage-Driven Test Cases Using IMC Rank

Peiqian Chen
UNISOC

Track 7 - AI-Driven Verification and IP Functional Signoff

08/19/2025 13:00 to
13:30

SW01_The Era of AI-Driven Verification - Agentic AI in Verisium Verification Platform

Rich Chang
Cadence

08/19/2025 13:30 to
14:00

SW02_Automated Simulation Regression Method and Application Based on SIM AI Technology

Feng Tian & Haohao Sun
Sanechips

08/19/2025 14:00 to
14:30

SW03_From MDV to MDAI AI-Enhanced Functional Verification with Verisium

Shawn Zhang
Analog Devices

08/19/2025 14:30 to
15:00

SW04_Verisium Debug Real-World Cases of SW/HW Simulation In Sanechips

Sihang Shang
Sanechips

08/19/2025 15:00 to
15:30

SW05_FPVIP: Formal Property Verification Framework for Packet Interfaces in Ethernet SoCs

Sihang Shang
Sanechips

08/19/2025 15:30 to
16:00

TEA BREAK

08/19/2025 16:00 to
16:30

SW06_Formal Verification Signoff Methodology for Pin Multiplexing Based on Jasper CONN

Chengzhe Li
UNISOC

08/19/2025 16:30 to
17:00

SW07_Accelerating Vector DataPath Optimization in Large-Scale AI Processor with Jasper C2RTL

Bowen Li & Hexin Bao
KUNLUNXIN

08/19/2025 17:00 to
17:30

SW08_Chiplets as an Enabler for Shorter Time-To-Market (TTM)

Sylvain GUILLEY
Secure-IC

Agenda Page

中国用户大会 2025年08月19日丨上海浦东嘉里大酒店

AGENDA

AGENDA

Track 1 - Custom Analog Design

CA01_The Future Is Now: Technology Breakthroughs for the Virtuoso Studio and Spectre Simulation Platforms

CA02_Application of Virtuoso Schematic Migration in Analog Circuit Migration

CA03_Method of Decreasing Memory Consuming and Improving Capability for Multi-Tone Simulation from Cadence Spectre RF

CA04_Application of Spectre X GPU in Large-Scale Analog Circuit Simulation

CA05_Virtuoso APR for Stdcell: The Most Anticipated Automatic Placement and Routing Flow

CA06_Application of FMC SmartCorner Based on ML Algorithms in the Project

CA07_SRAM Simulation and Verification with Spectre FX Simulator

TEA BREAK

CA08_Advanced Parasitic Analysis Solution to Speed Up Post - Simulation Convergence

CA09_Optimizing PLL Transient Simulation: An Efficient Measurement Method Based on PLLMeasure

CA10_Accelerating Simulation Verification for High-Precision Large-Scale Analog Design Circuit Using Spectre X-GPU Simulator Engine

CA11_Application of S-Parameter Quality Checking and Fitting Tool in the High-Speed Circuit Simulation Flow

Track 2 - Digital Design and Signoff

DD01_Digital Design Implementation Innovation Roadmap

DD02_Early Power Planning and Rapid Implementation Flow Based on Cadence Innovus FlashPG

DD03_Application of Voltus Insight AI in Physical Implementation of High-Performance CPU Cores

DD04_Efficient Clock Tree Synthesis Method and Application Based on Innovus COD

DD05_Research on IR Drop Optimization for Advanced Process ASICs Based on the Voltus-Insight AI Flow

DD06_Optimization Strategy of X-State Based IR Drop in Voltus

TEA BREAK

DD07_Accelerating Product Design Leveraging Cadence Managed Service in the Cloud

DD08_Quick PBA Timing Evaluation and Optimization Methodology for Critical Deep Logic Paths

DD09_Signoff Application Based on Llitmus-Xcelium Static Timing Constraint File

Track 3 - AI for Digital Design

AD01_Design for AI, AI for Design

AD02_SoC PPA Improvement with Combined Optimization of Turbo3 and Cadence Cerebrus in Genus and Innovus

AD03_Application of Joules-Based FlashReplay and XReplay in Place-and-Route (PR) Implementation

AD04_IR Drop Auto-Fix Based on Voltus InsightAI

AD05_Generative-AI Technology for Block and SoC IR Closure: Root-Cause and Repair Strategies

AD06_Accelerating the Realization of Physical AI Chiplets

TEA BREAK

AD07_Introducing Conformal-AI Studio – AI Acceleration for Logic Equivalence, Functional ECOs, and Low-Power Signoff

AD08_Efficient Collaborative Design and Verification Methodology for Multi-Bit Flip-Flops (MBFF) Based on Cadence Innovus and Conformal Tools

AD09_Tackling the Rise of SDC in AI Processors with Health and Performance Monitoring

Track 4 - System Analysis

SA01_Accelerating Innovation: AI-Driven Advances in Sigrity, Clarity and Optimality

SA02_Research on Distributed Power Network Noise Simulation Methodology Based on Cadence Software Platform

SA03_How to Complete the Simulation and Design of 112Gbps Channel with Powerful "AI"

SA04_Differentiate with Cadence IP and SoC Design & Embedded Services

SA05_Effective Optimization for Packaging Design of RF Modules by Optimality AI

TEA BREAK

SA06_Application of VRF for High-Speed Co-Design of PKG and On-chip Passive Device and Trace

SA07_Simulation Methods and Optimization Design of LPDDR5

SA08_Channel Performance Optimization of UCIe Based on Clarity Routing Model Generation Scripts

Track 5 - System Design and Thermal Solution

SD01_System-Level Design, Powered by AI

SD02_Cadence IP Overview – Accelerate AI Innovation with Cadence Silicon Solution

SD03_Cadence - Windchill Component Data Exchange

SD04_PCB and Busbar E/T Co-Simulation

SD05_3D PCB Connection Check Based on OrbitIO

TEA BREAK

SD06_Accelerating Aerodynamics: GPU-Powered CFD Simulation Workflow

SD07_Designing and Simulating Next-Generation Data Centers and AI Factories with Cadence and NVIDIA

SD08_Automatic Simulation Tool to Accelerate PCB Interconnection Verification

Track 6 - System Verification Solution and Methodology

VE01_Broadening the Adoption of Hardware Emulation with Next-Generation Emulation Appliance

VE02_EMU Full-Scenario AVIP Rapid Iteration Verification Solution for XR Chip

VE03_Power Analysis of AI Chip with Palladium DPA

VE04_Research on Accelerating Chiplet System-Level Verification with Distributed Simulation Technology

VE05_AP Chip Performance Verification Based on Palladium Platform

TEA BREAK

VE06_Optimization Techniques for Accelerating Gate-Level Simulation Using Xcelium: A NOACG and Fine-Grained Access Control Approach

VE07_Metrics-Driven Verification Solution Based on vManager

VE08_Optimization of Coverage-Driven Test Cases Using IMC Rank

Track 7 - AI-Driven Verification and IP Functional Signoff

SW01_The Era of AI-Driven Verification - Agentic AI in Verisium Verification Platform

SW02_Automated Simulation Regression Method and Application Based on SIM AI Technology

SW03_From MDV to MDAI AI-Enhanced Functional Verification with Verisium

SW04_Verisium Debug Real-World Cases of SW/HW Simulation In Sanechips

SW05_FPVIP: Formal Property Verification Framework for Packet Interfaces in Ethernet SoCs

TEA BREAK

SW06_Formal Verification Signoff Methodology for Pin Multiplexing Based on Jasper CONN

SW07_Accelerating Vector DataPath Optimization in Large-Scale AI Processor with Jasper C2RTL

SW08_Chiplets as an Enabler for Shorter Time-To-Market (TTM)

中国用户大会
2025年08月19日丨上海浦东嘉里大酒店