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August 19, 2025
08/19/2025 13:00
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Zhong Fan
Cadence
08/19/2025 13:30
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设计在不同工艺节点之间的迁移是每位IC设计师都非常关注的热点问题。为了帮助IC设计师解决这一问题，Cadence携手全球各大晶圆代工厂，开发出新的技术，以高效地将电路图迁移到新的节点，并使用更新的分析工具来确保获得最佳结果。Virtuoso Studio Migration是virtuoso studio IC23.1中基于Schematic XL的一个先进的电路迁移平台。可以帮助工程师快速的将自己的设计在不同工艺间进行迁移，以大幅度缩减电路设计周期，提高研发效率。该工具不仅支持多个library之前的协同迁移，同时也支持电路顶层的hierarchy迁移，在不同晶圆厂商工艺间迁移时也能自动解决net错位的问题。本文针对本公司一些实际的电路，基于该工具实现了在不同工艺间的迁移，大大提高了相同电路不同工艺间的复用效率，很大程度节省电路设计工程师对电路手动迁移所花费的时间。综上，前端工程师可以利用migration实现更多工作，大幅度提高工作效率，缩短项目交付周期。
Shengli Fang
Sanechips
08/19/2025 13:50
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With the rapid development of RF communication technology, large-signal simulation analysis of RF integrated circuits is facing increasingly complex challenges. To accurately simulate the complete signal spectrum, it is necessary to introduce multiple signals simultaneously and perform overlapping analysis in the simulation model. However, as the number of signals increases and the requirements for analysis precision improve, the memory resources required for simulation grow exponentially. Moreover, RF circuit signals are highly sensitive to peripheral metal coupling effects, requiring the introduction of complete metal trace S-parameters in modeling, which imposes higher demands on S-parameter accuracy. This study employs the Cadence Spectre RF flow, utilizing memory estimation and low memory technologies to optimize memory configuration for RF large-signal simulation. Simultaneously, the hb-xdp technology is applied to achieve distributed simulation, significantly reducing memory request of host. Combined with S-parameter Checking & Fitting technology to optimize S-parameter, this approach enhances hb simulation convergence. This article discussed how to use these technologies to achieve complex and precise large-signal harmonic simulation effectively.
Yunpu Zhang
UNISOC
08/19/2025 14:10
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随着先进半导体工艺节点的不断演进，模拟集成电路设计面临着器件规模爆炸式增长与寄生参数复杂度提升的双重挑战，基于CPU的Spectre X仿真器在算力需求与硬件资源之间的矛盾日益凸显。为突破这一技术瓶颈，Cadence公司推出基于GPU加速的Spectre X仿真功能，利用GPU强大的并行计算能力，在确保仿真精度的同时显著提升计算效率。实验结果显示，在多种工艺节点下的典型模拟电路设计中，相较于传统CPU集群方案，GPU加速模式在百万级晶体管规模的电路仿真任务中实现了高达8倍的性能提升，展现出GPU技术在大规模模拟仿真中的巨大潜力。
Kaibin Zhang
Sanechips
08/19/2025 14:30
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The article discovers the future of layout design with the Virtuoso Automated Standard Cell Placement and Routing Flow. This cutting-edge solution integrates the powerful Innovus GigaPlacer and NanoRoute technologies within the Virtuoso platform, revolutionizing the way you approach standard cell placement and routing. This article contains:
Why Virtuoso?
Unmatched Efficiency: Virtuoso's automated flow significantly reduces manual intervention, streamlining the entire process from schematic design to final routing. With the ability to handle designs with up to 2,000 instances, it ensures rapid and accurate layout generation.
•User-Friendly Interface: The Auto P&R assistant and Routing assistant provide an intuitive, easy-to-use interface that simplifies complex tasks. Whether you're setting up the environment, placing cells, or configuring routing, Virtuoso makes it effortless.
•Comprehensive Features: From creating width spacing patterns (WSPs) and placement rows to generating supply grids and IO pin planning, Virtuoso covers all aspects of standard cell placement and routing. The flow ensures LVS correctness and DRC compliance, delivering high-quality design outcomes.
• Advanced Analysis Tools: The Routing Results Browser allows you to view and analyze routing results in detail, helping you identify and resolve issues quickly.
Session Highlights:
• Environment Setup: Learn how to configure your design environment for optimal performance.
• Automated Placement: See how the Auto P&R assistant automates the placement of standard cells, boundary cells, tap cells, and filler cells.
• Routing Configuration: Discover how to set up the standard cell router, assign wire types to nets, and generate supply grids.
• Routing Execution: Watch live demonstrations of signal routing and result analysis using the Routing Results Browser.
Join us to see how Virtuoso can transform your layout design process, making it more efficient, accurate, and user-friendly. Don't miss this opportunity to learn from industry experts and experience the power of Virtuoso firsthand.
Yonggui Zhang
ESWIN
08/19/2025 14:50
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在先进工艺快速迭代并且良率受到较大挑战的情况下，如何用最少的资源保证模块的良率也越来越关建，而通过多sigma，以及多corner的MC验证可以辅助我们加快验证，更大程度的减小成本，增加产品的竞争力。现有流程通过standard MonteCarlo进行验证，在多sigma，并且电路修改的情况下进行standard MC验证，针对时间以及服务器资源成本消耗较大；尤其是多sigma叠加多corner的情况下需要验证与corner数成倍数的点数，而验证较少的点数不符合统计学规律，针对良率验证不能充分保证；cadence FMC smart corner 基于AI算法，在保证精度的情况下，在多corner中找到worst case，优化MC验证点数，减小仿真时间以及服务器成本，有效的加快了设计迭代效率。
Xingbo Yang
Sanechips
08/19/2025 15:10
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随着集成电路技术节点的进步，存储电路例如SRAM的电路设计日益复杂，电路规模也不断增大，后仿寄生效应对电路功能的影响愈加显著，这对仿真器的容量、性能和精度都带来了巨大的挑战。SRAM通常具有高速、低功耗等特点，在消费电子、计算机、工业与医疗领域被广泛应用。对SRAM电路的验证要求涵盖功能、时序、功耗、可靠性等多个方面。这对仿真器的功能及对全流程的支持能力提出了更高的要求。
SpectreFX作为Cadence最新一代的FastSPICE仿真器，它采用了全新的逻辑架构，优化的电路划分算法，能针对大规模电路进行快速仿真，并且具有高效的多核扩展能力。经过了五年的市场考验，已经证实了在不同工艺节点，不同类型的电路，前仿、后仿中都能获得较大的仿真速度提升，也早已被广泛应用于SRAM电路的功能、时序和功耗验证。通过SpectreFX的多种预设模式，设计工程师可以根据实际需求，十分方便地获得仿真速度与精度的平衡，不再需要额外调节仿真设置。在此基础上，SpectreFX还支持Circuit Check、Reliability Analysis、MonteCarlo Analysis、EMIR Analysis等各种功能，为提高SRAM设计的可靠性和良率提供了全面的仿真与验证解决方案。
本文将介绍SpectreFX在SRAM设计全流程中的应用, 分享我们在SRAM项目中使用SpectreFX进行功能、时序、功耗仿真，并使用Circuit Check、Reliability Analysis、MonteCarlo Analysis、EMIR Analysis等进行全面可靠性验证的经验。
Shoudao Wu
UNISOC
08/19/2025 15:30
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08/19/2025 16:00
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In the realm of semiconductor design, achieving efficient post-layout convergence and accelerating ECO iteration processes are critical challenges. Quantus Insight is a powerful tool that enables users to analyze, debug, and optimize extracted DSPFs or I-DSPFs in a fast and interactive manner. Users can employ Quantus Insight to perform various types of analyses, including single-net, multi-net, single DSPF or I-DSPF, and multi-DSPF or I-DSPF analyses for point-to-point (p2p) resistances, total and coupling capacitances, and delays. The tool provides two main modes: the Analyzer mode, which analyzes nets within a DSPF or I-DSPF, and the Comparator mode, which compares nets between two DSPFs or I-DSPFs.
Users can launch Quantus Insight from the command line or within Virtuoso by selecting the Quantus Insight menu from Virtuoso layout or schematic view.
The tool's ""what-if"" functionality plays a pivotal role in facilitating post-layout convergence by allowing designers to explore various scenarios and their impacts on the design. This capability significantly enhances the ECO process, enabling rapid and informed decision-making to optimize the design.
Quantus Insight also provides additional benefits, including the ability to analyze the required topology changes for an ECO to meet the design specification, visualize the network to understand the implications of physical topology in circuit design space and physical layout space, and probe the schematic, both flat and hierarchical, by loading the Interactive DSPF (I-DSPF) view. Furthermore, the tool allows users to enable or disable and read Virtuoso constraints, which is synched with the Virtuoso Constraint Manager.
Da Cheng
Amlogic
08/19/2025 16:20
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As technology continues to evolve, circuit design specifications are becoming increasingly stringent, making the efficiency of jitter measurement in PLL design particularly important. Currently, when performing PLL transient simulations with Cadence APS/Spectre X simulators in their default settings, some additional jitter may be introduced due to simulation methods and accuracy choices, which do not reflect the actual behavior of the circuit. This not only affects the accuracy of the simulation results but also introduces uncertainty in the design verification flow. Additionally, for new PLL designs, users need to experiment with various accuracy settings to find a more reliable and stable locking frequency. However, manually adjusting accuracy makes it difficult to control the performance of the PLL frequency under different accuracy settings, and optimizing simulation step size, measurement result accuracy, and simulation time becomes complex. These issues significantly impact the efficiency and iteration rate of users in PLL simulations, increasing the design cycle and costs.
To address these user concerns, Cadence offers a new flow called PLLMeasure. This flow not only significantly enhances simulation stability but also eliminates the tedious task of manually adjusting accuracy to find suitable settings for PLL transient simulations. By automatically optimizing accuracy settings, PLLMeasure can maximize the reduction of repetitive work for engineers in simulation tasks. Additionally, it provides multiple jitter measurement results for designers to verify after the simulation is complete, without requiring users to write jitter measurement formulas to recalculate results. This not only improves simulation efficiency but also ensures the accuracy and reliability of the results, making the design flow smoother and more efficient.
Xiang Zhao
ASR
08/19/2025 16:40
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随着集成电路规模和设计复杂度的不断升级，特别是先进工艺后仿中存在的更加复杂的器件模型、指数级增长的寄生参数以及大量需要签核的工艺角，给电路仿真验证带来了极大挑战。传统基于CPU的模拟电路仿真器面临计算效率瓶颈，GPU加速技术逐渐成为突破这一困境、提高验证效率的核心路径之一。
模拟电路仿真中庞大的矩阵求解，复杂的模型评估，解算过程中的多次迭代及高精度收敛标准，对仿真器的计算能力和准确性提出了极高的要求。SpectreX-GPU是Cadence Spectre平台一款新的全精度SPICE仿真引擎，将传统的基于CPU的电路仿真工具拓展至更大算力的CPU-GPU异构系统中，结合了GPU强大的并行计算能力与CPU的复杂计算能力，实现两种计算能力之间的高效调度和平衡，同时保持SpectreX仿真器的准确性。利用SpectreX-GPU可以完成过去无法仿真或需要很长时间才能完成的仿真，极大地提升了先进工艺大规模高精度复杂电路的仿真验证效率，突破了该类设计的仿真验证瓶颈。同时，SpectreX-GPU支持分布式作业调度系统，并且已经集成到Virtuoso ADE，用户可以在Virtuoso ADE图形界面从SpectreX无缝切换到SpectreX-GPU，简单易用。
本文针对本公司不同工艺节点以及不同类型的实际电路，尤其是大规模高精度模拟电路，利用SpectreX-GPU进行仿真，与基于CPU的SpectreX相比，在不影响仿真精度的前提下，显著缩短了仿真时间，提高了验证效率和覆盖范围，帮助在保证设计质量的前提下进一步缩短设计周期。
Chaolin Zhang
UNISOC
08/19/2025 17:00
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在高频高速电路设计中，对电感、传输线等无源器件、关键长走线或封装结构进行电磁场仿真并提取S参数，是确保信号完整性、降低设计风险的核心手段，因此S参数被广泛应用于高频和高速电路设计中。设计人员使用电磁场仿真器提取关键器件、走线或封装的S参数，带入实际电路进行仿真验证和设计迭代。而在仿真过程中，经常会遇到带S参数的仿真不能收敛或者结果不准确的现象，问题根源难以定位，极大地影响了迭代优化的效率。Cadence SPECTRE 仿真器的S-Parameter Quality Checking and Fitting Tool可以对S参数文件进行快速准确分析，并给出清晰且可视化的S参数检查结果，也可以对S参数进行拟合修正。该工具支持图形界面和命令行，支持批量检查/修正多个S参数，可以对修正前后的S参数进行对比，可以单独使用，也可以通过debug option在仿真时被间接调用，方便易用，灵活性大，可以帮助快速定位S参数引起的仿真问题，避免无效的长仿真，从而有效提升高频和高速电路的仿真效率。本文介绍了一个实际案例，在带S参数的仿真中遇到了收敛问题，调整仿真器的设置无法解决该异常。工程师利用该工具，发现了S参数的品质缺陷，针对该缺陷改进提取设置并重新抽取S参数后，收敛问题得到了有效解决。
Bo Zhang
Sanechips
08/19/2025 13:00
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The presentation outlines the advancements and strategic direction for Cadence's digital design and signoff solutions. The roadmap highlights key innovations, including pervasive AI-driven engines, and integrated synthesis and implementation flow, early detail routing etc. The presentation also covers the introduction of Innovus+™ 25.1, emphasizes the role of AI in optimizing placement, power, and timing, as well as the integration of Python user interfaces for AI data analytics. The comprehensive solutions aim to provide fast design closure and enhance designer productivity.
Yufeng Luo
Cadence
08/19/2025 13:30
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在IC后端设计中，电源网络（PG）结构的实现对芯片性能和可靠性至关重要。使用Cadence Innovus的Flash PG引擎可显著提升设计效率，尤其在缩短实现时间和减少DRC违例方面表现突出。与传统方法相比，Flash PG流程通过读取完整的PSDL文件，调用Innovus内置的Flash PG引擎，一次性生成完整的PG网络，大幅减少人工干预。Flash PG流程可将电源网络生成速度提升至传统方法的10倍，尤其在顶层设计中优势更为明显。Flash PG的完整模式不仅生成PG网络，还会主动检测并修复金属层间距、通孔对齐等DRC问题，避免传统流程中因手动操作疏漏导致的违例。且工具可动态补强IR Drop薄弱区域的电源网络，该方法可修复66%的动态IR Drop违例。Flash PG结合Early Rail Analysis（ERA）技术，可以在设计的初期实现电源网络可靠性评估和优化，从而提升PPA 的指标。 Flash PG和ERA的协同分析，实现了电源网络“生产-分析-优化“ 一体化流程，显著提升了设计效率和芯片的可靠性，尤其适用于高性能（HPC）与AI 芯片等对功耗敏感的场景。对于追求高性能与高可靠性的芯片设计，这一工具已成为实现PG结构的首选方案。
Guangzheng Xiao
Sanechips
08/19/2025 13:55
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随着高性能计算芯片设计向先进工艺节点演进，芯片集成度的飞跃式增长使得晶体管密度突破每平方毫米数亿门级，导致电源分配网络（PDN）的金属线宽持续收窄，通孔电阻呈非线性上升，加上高密度逻辑单元在GHz级时钟频率下的同步翻转行为，显著加剧了电压降（IR Drop）风险。本文基于Cadence Voltus Insight AI feature，提出了一种针对高性能CPU核的物理实现的全流程电压降优化方案，通过整合AI驱动的IR感知布局（IR-Aware Placement）、电源网格修复（Power Grid Fixing）及Watch Box修复技术，能够动态预测电源网格的电流分布热点，对高功耗逻辑单元进行摆放优化，实现IR 热点区域的提前预防和高效修复。结果表明，在相同条件下，不仅能节约时间，提高效率，电压降修复率也过去的66%显著提升至96%，同时避免了时序（Timing）与设计规则（DRC）的恶化。
Shu Jiang
Jaguarmicro
08/19/2025 14:20
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时钟树综合时数字芯片物理设计工作中的重要一环，其质量情况可以直接决定时序收敛的状态与模块整体的功耗情况，利用innovus中的ccopt_design(COD)可以方便的对时钟树进行构建，spec文件是时钟树综合过程中重要的引导性文件，常用的spec文件通常由工具基于约束文件(SDC)生成，完全基于SDC生成的spec文件不一定是最合理的，对于时钟结构复杂的模块需要大量人为干预spec文件，但工具自动生成的spec文件通常难以阅读，中间存在大量冗余的部分，不利于用户进行调整，因此需要建立一个标准来规范spec文件，不仅从其格式或内容顺序上进行约束，同时更要对冗余的部分进行精简。
本文中基于对不同类型的时钟结构进行分析，提出了一种规范化的spec文件，通过脚本实现对工具生成的spec文件的调整与重组，精简了原spec文件中冗余的部分，增加了spec文件的可读性，并添加了相关接口，方便用户直接在spec文件中添加或删除相关的设置，以更高效、更便捷的对时钟树综合过程进行管控与分析。基于规范化的spec文件能够更为直接的避免无效balance，从而缩短时钟长度，降低时钟上的功耗，对于时序收敛与功耗控制具有重要的意义。
Aolin Li
Sanechips
08/19/2025 14:45
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随着工艺节点的不断演进，芯片的集成度越来越高，这将使得功耗密度也愈来愈大，芯片供电网络的电阻也逐渐增大，此外设计的复杂度和频率也同步提升，导致电源压降越来越成为制约高性能模块实现的关键[1-3]。因此，亟待解决的上述痛点成为研究者的重点关注方向，本文针对ASIC的多种高频高功耗模块，探索使用cadence的新技术来提高供电强度，优化芯片供电网络。Voltus-Insight AI通过对芯片物理实现过程中pre-route & post-route阶段功耗和IR drop分析，进行局部IR drop热点打散和强化供电网络，可有效优化IR drop违例，提高良率。本文基于Voltus Insight AI feature的应用，验证了在多种模块子系统上IR的优化效果，对于5G子模块的优化，将违例数量从7k vios降至约0.9k vios，优化幅度达到87%；对于CPU子模块的优化，IR违例从31k vios降到约0.8k vios，优化效果达97%。此外，可通过多次迭代优化进一步提高优化效果，并且在优化过程中对时序、DRC等维度不会造成恶化，有效修复IR违例。
关键字：ASIC; IR Drop; Voltus-Insight AI;
Zhen Liang
UNISOC
08/19/2025 15:10
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Voltus Insight-AI 是一种电源网络（PG）自动化修复工具，旨在解决集成电路设计中的电压降（IR drop）问题。该工具能够在保证时序和物理设计规则检查（DRC）的前提下，有效优化电源网络，降低 IR drop。在大规模设计中，Voltus Insight-AI 能够显著减少人工干预，加速自动布局布线（APR）流程中电源网络的增强和 IR drop 违例的修复。
随着先进工艺节点和复杂设计需求的增长，IR drop 问题日益突出。Voltus Insight-AI 的应用范围已扩展至多种工艺节点，以适应复杂多变的设计需求。本文以 16nm 和 40nm 工艺节点为例，探讨 Voltus Insight-AI 在处理低功耗设计中的 IR drop 违例方面的性能。研究对象包括块级电源门控（Block-Level Power Gating）和单元级电源门控（Cell-Level Power Gating，Daisy Chain）两种类型的电源开关。
通过对小型微控制器（MCU）和大规模微处理器（MPU）设计的分析，本文评估了 Voltus Insight-AI 在不同设计类型上的兼容性。研究结果表明，该工具能够在快速修复 IR drop 违例的同时，有效避免时序和 DRC 的恶化。
Shining Dong
NXP
08/19/2025 15:35
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08/19/2025 16:05
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This presentation covers how various companies in EDA and Systems space are accelerating their product design by leveraging Cadence Managed environment in the cloud. Many companies from start-ups to large companies are accelerating innovation, engineering productivity and time to tape-out by using scalability and flexibility offered by Cloud and this presentation will cover some of the examples from the industry. We’ll also cover the current advances and challenges for cloud migration including aspects of security in the cloud. Finally, the presentation will touch upon how customers can take advantage of the latest AI/ML enabled Cadence tools in the cloud and how Cadence Managed Cloud can optimize cost-efficiency and productivity for intelligent system design. You’ll learn how to harness the full potential of cloud technology to streamline your EDA and Systems workflows and achieve remarkable results.
Mahesh Turaga
Cadence
08/19/2025 16:35
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STA timing closure is always challenge task for SoC design. There’re two modes of STA timing analysis. – GBA(Graphic Based Analysis) and PBA(Path Based Analysis). GBA always calculates instance delay and output transition based on worst input transition. So GBA has fast run time but pessimistic timing. PBA calculates cell delay based on actual timing path. So PBA is accurate but taking longer time.
In design which includes critical timing paths with complex logic and deep depths, designer is always suffering long PBA run time. As for these paths, GBA pessimism is also large. So although timing is possibly satisfied in PBA already, designer need a long run time to get the result, or in some case, can’t get exhaustive result. Then very difficult timing fix is needed to get PBA result, though they’re over fix.
This paper introduces an innovated way to evaluate PBA timing quickly. The reason why the paths have large slack difference between GBA and PBA, is there’re bad transition pins causing large cell delay, but paths through these pins are not timing critical. The proposed method has 3 steps. 1. Search all input pins of all instances in violated paths, find pins with large transition (e.g. 500ps) but meet GBA timing; 2. Annotate these input pins with small transition (e.g. 10ps); 3. Report STA PBA timing. By this way, PBA analysis time is largely reduced.
In one MCU design (near signoff), original STA run time is more than 9 hours. With this method, STA run time is reduced to 1hour and 20 minutes.
This PBA evaluation method can also be used to estimate chip frequency in early stage. At that time, design is dirty and it’s not easy to get PBA result. So designer is always suffering to say if the aggressive frequency targe can be meet or not. This method can help designer to draw conclusion more quickly.
Glen Ge
NXP
08/19/2025 17:00
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Timing analysis is an indispensable step in the digital circuit design flow, playing a pivotal role in ensuring circuit correctness, performance, and reliability. To achieve reliable static timing analysis (STA) results, it is critical to verify the completeness and accuracy of SDC. However, with the escalating scale and complexity of modern designs , SDC validation increasingly relies on empirical expertise. This paper proposes a Cadence tool for SDC signoff ——Litmus, which integrates RTL/netlist inputs with constraint files for SDC signoff. The flow comprises three core phases: constraint linting, constraint signoff, and SVA (SystemVerilog Assertions) generation, which can effectively assist users in correcting errors within constraint files. Litmus demonstrates unique advantages over other tools like GCA (Generic Constraint Analyzer) , including detection of constraint overwrites, identification of port-clock mismatches, and SVA generation for user-friendly simulation validation.
Shuang Xue
Sanechips
08/19/2025 13:00
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AI adoption is growing at an accelerated pace driving silicon and systems complexity to new heights. While the number of chips being designed with AI-enabled tools is soaring, their time to market is shrinking. Cadence is leveraging AI agents, our deep expertise in principled simulation and optimization, and GPU acceleration to enable this revolution. What is the role of AI agents? How far can they take us? The future of chip design is happening now with Design for AI, AI for Design.
Ben Gu
Cadence
08/19/2025 13:30
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For SoC implementation, power, performance and area are always most important metrics for SoC physical designer. How to achieve better PPA in short turnaround time is big challenge today. To support designer for state-of-art design, Cadence introduces Turbo engine and Cerebrus AI tool for both logic and physical optimization.
This paper introduces design optimization flow with Turbo3 and Cerebrus in Genus and Innovus. Turbo3 is implemented first to increase frequency and recover instance area. After Genus generates mapped netlist, Innovus reads it directly and executes logic and physical combined optimization with POD Turbo3 engine for better PPA. After that, Cereburs AI is applied for further optimization with ML engine.
Compared to traditional PR flow, chip frequency hits 200Mhz target with 4% utilization reduction and 3% power reduction, based on combined optimization of Turbo3 and Cerebrus.
Bingqian Xu
NXP
08/19/2025 13:55
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Cadence 的 FlashReplay 和 XReplay 是两种用于硬件设计验证和调试的关键功能，各自针对不同的应用场景。FlashReplay 主要用于快速验证设计中的小改动，通过复用已有的仿真结果实现增量验证，从而节省时间并提高效率。它特别适用于在已有仿真基础上进行局部调整的验证需求。而 XReplay 则更侧重于在仿真过程中捕获和重放特定信号或事件，帮助设计人员深入分析问题根源，尤其适用于复杂调试场景。两者在功能定位和使用场景上各
Yuewu Yan
Sanechips
08/19/2025 14:20
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随着集成电路先进工艺节点的设计复杂性越来越高，EM-IR的系统分析和大量违例的快速修复成为挑战。作为集成于数字实现平台 Innovus 的AI驱动签核工具，Cadence Voltus InsightAI通过机器学习方法进行金属层的优化能够实现IR drop的自动修复。本文阐述了Cadence Voltus InsightAI工具在14nm 算力芯片设计项目中动态IR drop修复的应用实践。结果表明，该方法在保持PPA指标没有明显偏移与DRC违例增量较小的约束下， 成功实现IR drop违例修复率超过82%，相较传统人工流程减少了迭代次数、提升了修复效率。通过动态电压域分析与智能调整标准单元的摆放和电源线的排布，大大缩减了修复周期，为先进工艺下的功耗完整性签核提供了可扩展的自动化解决方案。
Xue Gong
VeriSilicon
08/19/2025 14:45
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Designers are regularly facing a significant number of EM-IR violations at signoff, making it imperative to address this challenge early in the design phase. Some of the challenges related to in-design EM-IR analysis:
Today’s methodology of IR-fixing which is mostly a manual process takes multiple weeks per block, with the discussed methodology IR fixing can be brought down to less than a day with high (>90%) fix-rate.
The Voltus InsightAI technology enables greater engineering efficiency for uncovering issues early and offers key productivity-enhancing features ensuring:
This paper will detail the evaluation of InsightAI technology (Cadence Innovus/Voltus tool) based advanced process design (5nm), including the changes in the flow, the PPA and productivity gains that can be realized by the application of the technology.
Siki Yang
Analog Devices
08/19/2025 15:10
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The semiconductor industry is undergoing a major transformation from traditional monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This shift aims to mitigate the complexities associated with scaling designs, optimizing yields, and addressing rising fabrication costs. Economic drivers, such as increasing transistor costs and diminishing returns from Moore’s Law, are fueling this transition. To navigate this change, the industry needs advanced solutions that address a wide range of system requirements and facilitate efficient design through integrated architecture, tools, flows, and system IP.
In this joint presentation, discover how to expedite your Physical AI, including Automotive, SoC designs with Cadence’s advanced chiplet-based platform, in collaboration with Samsung. The industry is currently witnessing the convergence of two seemingly opposing trends: the move towards high-performance, centralized computation (e.g., enabling software-defined vehicles) and the disaggregation of computation into discrete chiplets that can be independently verified and certified. Cadence’s multi-chiplet-based architecture addresses both demands by incorporating high-performance compute chiplets and ensuring multi-die interoperability. In this presentation, we will unveil our Physical AI Chiplet platform in design, in collaboration with Samsung, including a framework for system and safety management, addressing the needs of a multitude of Physical AI designs including Automotive Advanced Driver-Assistance System (ADAS), drones and robotics applications.
Michael Posner
Cadence
08/19/2025 15:40
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08/19/2025 16:10
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With artificial intelligence and machine learning (AI/ML) capabilities, Conformal AI Studio directly addresses the increasing productivity demands of modern SoC teams. This is achieved through core engine speedups, new algorithm innovations, and simplified setups and AI-enabled flows for LEC and ECO solutions. New ML-driven abort resolution tackles the most complex LEC problem advanced users face today. Conformal AI Studio delivers an order of magnitude higher designer productivity and smaller and faster ECOs and enables optimal full-flow power, performance, and area (PPA) by supporting the most advanced implementation tool optimizations. Come learn about the next generation of Conformal!
Wells Jong
Cadence
08/19/2025 16:40
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本文针对高性能集成电路设计中多比特单元（如寄存器、数据路径模块）的实现和验证挑战，提出了一种基于Cadence Innovus物理设计工具和Conformal逻辑等价性检查工具的高效协同工作流程。利用Innovus的多目标优化引擎，该方法在布局布线阶段实现了面积、时序和功耗的协同优化，使关键路径延迟平均减少15%，动态功耗降低20%。通过Conformal工具在RTL级和门级网表之间进行形式等价性检查，确保功能一致性，验证周期减少30%。该框架的有效性在一个先进节点流片项目中得到验证，定制化的自动化脚本最大限度地减少了人工干预，提高了设计可靠性。该解决方案显著提高了复杂模块的设计效率，为高密度芯片设计提供了可重用的技术策略，并通过加速产品上市时间和降低研发成本，提供了关键的行业价值。
Sheng Yang
Sanechips
08/19/2025 17:05
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Silent Data Corruption (SDC) poses a growing threat to AI processors, escaping conventional detection methods and undermining hardware reliability. As AI workloads become more compute-intensive, undetected processor faults can lead to incorrect computations, cascading failures, and unpredictable system behavior. Traditional silicon testing methods, including scan, ATPG, and functional testing, fail to catch the subtle anomalies that cause SDC, making in-field monitoring essential. With hyperscalers reporting hgher SDC rates, the need for a proactive, multi-stage detection approach has never been more critical.
proteanTecs introduces a two-stage solution to combat SDC: telemetry based Outlier Detection, which enhances SoC testing with ML-powered parametric analysis to identify at-risk chips before deployment, and Real-Time Health Monitoring (RTHM), which continuously tracks chip performance in the field to detect and prevent emerging faults. By leveraging deep data insights, real-time monitoring, and predictive analytics, proteanTecs' technology reduces SDC occurrences, enabling AI processors to maintain reliability at scale. This approach shifts the paradigm from reactive troubleshooting to proactive prevention, ensuring that AI systems can operate with high integrity and confidence.
This presentation will review the Cadence implementation workflow for integrating proteanTecs on-chip monitoring solution, in use today at leading semiconductor companies. Leveraging Cadence tools, novel methods are employed to implement proprietary Agents (IP). As a provider of both soft and hard IPs that are inserted into an existing functional design, proteanTecs streamlines the integration process by the user through the use of Cadence solutions. This collaboration delivers a holistic approach to ensuring AI processor reliability in the face of increasing complexity.
Dragon Hsu
proteanTecs
08/19/2025 13:00
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The next generation of electronic system design demands speed, accuracy, and intelligent automation. In this speech, I will introduce the latest breakthroughs in the upcoming Sigrity, Clarity, and Optimality releases, highlighting how AI-driven technologies transform simulation, optimization, and design generation. From rapid model acceleration to advanced design space exploration, discover how our integrated AI infrastructure enables customers to achieve higher performance and productivity in complex electronic designs. Join us to explore real-world examples and learn how these innovations empower engineers to meet the challenges of tomorrow’s systems, today.
Jian Liu
Cadence
08/19/2025 13:30
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为了缩短采用PowerSI提取电源S参数的建模时间，提高芯片内部功能模块电源仿真的精度，进一步降低电源噪声，引入了一种基于封装电源的分布式建模及电源噪声实测点确定方法。用该方法研究了系统处理芯片内部功能模块的电源仿真，发现在时域电源仿真的噪声中，同一数据流流经功能近似的电源模块产生的电源噪声存在相似性。在此基础上，建立封装多端口电源分布式模型，将功能近似的电源模块进行分组，并将分组后的封装电源S 参数模型和die内RC模型融入到基于Virtuoso的电源时域噪声仿真中，然后根据仿真结果确定封装bump处最大电源噪声实测点的位置。通过仿测对比发现，在噪声频域主频点对齐的条件下，噪声时域的仿测误差小于10%，验证了所提仿真方法的有效性。
Jin Zhang
Sanechips
08/19/2025 14:00
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随着高速串行信号速率的不断提升，目前112G速率的产品慢慢成为主流，在如此高的速率下，对工程师的PCB设计和仿真的要求和难度都变得越来越大。本论文将利用一个具体的产品案例，向大家展示如何通过cadence下的optimality这个AI强大的仿真模块进行112G链路的高效优化过程。
我们知道，链路的仿真分为无源仿真和有源仿真，无源仿真以保证链路的TDR阻抗及插入损耗回波损耗为主，而有源仿真则加入芯片的模型进行眼图及误码率的仿真，两者相辅相成，共同保证高速链路的质量。
本论文首先通过仿真测试拟合来验证这款3D无源仿真软件的精度后，然后分别在无源仿真和有源仿真下各自使用optimality，先搭建链路的仿真模型，在多个链路固有阻抗不连续点的情况下，先利用有源的optimality仿真锁定最佳的走线阻抗值，然后再根据目标阻抗去进行像BGA、光模块连接器扇出等复杂结构的无源optimality阻抗优化，从而保证链路的阻抗一致性，继而保证整个PCB链路的质量。在整个过程将在cadence的“AI力量”下完成，优化思路非常清晰，仿真优化过程不仅快速且性能优越，比起传统来回迭代的仿真方案更凸显它的高效性，可以帮助产品周期更快速进行推出和迭代。
Gang Huang
EDADOC
08/19/2025 14:30
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As Design Complexity increases and Foundry Nodes decrease below 12nm/7nm: the risks of failure increases multi fold. You need a strong Design partner who has strengths in IP’s and Chiplet Designs.
SoC design from spec to GDSII and package design is a complex and iterative process that requires a deep understanding of both hardware and software, as well as advanced design tools and methodologies. The presentation gives an overview of Cadence capabilities in this domain.
Bhaskar Kolla
Cadence
08/19/2025 15:00
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Shiyun Zhou
UNISOC
08/19/2025 15:30
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08/19/2025 16:00
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In the rapidly evolving landscape of CMOS RFIC and high-speed circuit design, the demand for high-bandwidth, high-frequency applications has reached unprecedented levels. The close proximity of on-chip top metal and package results in substantial parasitic coupling and electromagnetic interference, which can severely impact signal integrity. Moreover, bumps plays a important role, which is always neglected in the conventional approach of designing passive device and trace on chip and package independently. The intricate interplay between these components necessitates a holistic design strategy. Cadence's Virtuoso RF Solution combines a series of pivotal tool, such as Virtuoso, Clarity, Allegro, offering an integrated platform for the co-design of packages and on-chip passive devices and traces. This paper introduce an application of VRF Flow for a extreme-high-speed design, achieving an ideal frequency response curve and reducing the gap between simulations and measurements.
Haowei Lu
Sanechips
08/19/2025 16:30
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LPDDR5X的仿真在整体上包括两个部分，S参数的提取和时域波形的仿真。S参数的提取需要结合实际的工程情况进行设计，除了常规的PCB的叠层和走线之外，还应该包括焊球的规格，点胶的材料等信息。
Fanpeng Cao
NIO
08/19/2025 17:00
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随着Chiplet技术逐渐成为突破单芯片性能瓶颈的关键路径，UCIe 的重要性日益凸显，同时也对其物理层设计提出了更高的要求。相较于标准封装，基于硅中介层（Si-interposer）的先进封装为SI工程师提出了更严峻的挑战：硅中介层以mesh网格拓扑结构为主，导致参考地层不完整、电磁耦合路径复杂化，进而显著增加建模与优化难度。在此背景下，如何快速优化UCIe走线设计以获得较优的SI性能，成为工程实践中亟待解决的一个问题。本文基于Clarity走线模型生成脚本，以频域特性为指标，在五层硅中介层工艺条件下，进行了UCIe走线pattern优化，设计了一种性能较优的四层异构走线pattern，并使用Innovus完成了die-to-die互联的物理设计。提取实际设计的S参数模型后，利用Topology Workbench完成了时域眼图仿真验证。实验结果表明，优化后的UCIe互连走线方案在时域与频域均展现出优异的通道性能，可为高密度Chiplet集成提供设计参考。
Erling Pan
Sanechips
08/19/2025 13:00
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As AI becomes pervasively embedded in the products from Cadence, Allegro has embraced both Optimization and Generative AI methods to enable the highest productivity for users with lowest Turn Around Time and higher Quality of Results. Integration of Analyses with System level design is now imperative for high quality designs to be delivered to meet the time to market goals in the industry. The presentation illustrates the capabilities that have been developed and planned in Allegro X.
Saugat Sen
Cadence
08/19/2025 13:30
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Arno Li & Wei Wang
Cadence
08/19/2025 14:00
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在电子设计中, 元器件选型是一个复杂且耗时的任务。ECAD Designer需要确保设计中选用的器件既能满足设计要求，同时又满足公司供应链管理的要求。ECAD Designer需要同时看到Cadence Library Database中的数据和Windchill 中电子元器件的参数信息来进行元器件选型。为了帮助工程师在设计中高效的筛选到所需的元器件并快速加入到原理图中，我们通过Cadence Pulse Library Synchronization模块功能，实现 Windchill与Cadence数据库定期同步，方便用户在ASC（Allegro System Capture）的Unify Search中看到来自Windchill的数据，并便捷地根据参数类型和参数内容过滤筛选，快速地将元器件模型加入到原理图进行原理图及PCB设计。
Jackie Yan
Schneider Electric
08/19/2025 14:30
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案例针对汇流排与PCB双重供电结构的电热仿真，应用cadence Celsius仿真平台实现此类多种构成的电热仿真，仿真结果与实测做了对比，显示契合度较好。
Dan Wu
H3C
08/19/2025 15:00
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手机空间越来越紧凑，旗舰手机主板往往使用3D堆叠的方式来缩小PCB尺寸提高整机空间利用率。3D堆叠主板可分为下板、框板和上板，它们通过焊点焊接的方式连接在一起实现主板功能，保证焊点位置和信号名一致在设计中至关重要。本文介绍通过使用OrbitIO实现自动检查下板、框板和上板焊点位置和信号名一致性的方法，提升了检查设计效率和准确性，同时利用在OrbitIO调整后反标回brd文件的功能实现快速调整。
Xin Li
HONOR
08/19/2025 15:30
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08/19/2025 16:00
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Zhouqiao Zhao
BETA
08/19/2025 16:30
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随着生成式 AI、代理式 AI和物理 AI的爆发式增长，新一轮工业革命已经拉开帷幕。企业正在从传统数据中心转向一种新型数据中心 —— AI工厂。了解AI工厂的作用，以及设计、建造和运营这些新设施所面临的挑战。探索由NVIDIA Omniverse 、OpenUSD 和 Cadence Reality Digital Twin支持的先进物理仿真如何帮助数据中心团队以更高的效率和更优的性能大规模设计这些复杂的 AI工厂。了解更广泛的数据中心生态系统如何支持这些创举，并加速各行各业和各领域的人工智能。
Scott Fu
NVIDIA
08/19/2025 17:00
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PCB互连设计的SI/PI仿真验证过程中，往往需要工程师根据仿真结果对设计进行若干轮的优化迭代。而对于同一芯片平台的同一信号接口、电源，无论板级互连设计如何变化，或者一个全新的板级互连设计，配置参数、建模、整理结果数据等针对仿真软件的操作一般都是共通的，即仿真工程师在做大量机械重复的工作，设计验证的效率还有提升空间。
本文基于Sigrity的API（Application Programming Interface）和TCL（Tool Command Language），完成一套支持多种高速信号接口和电源板级频域仿真的SI/PI自动化仿真工具。只需输入仿真的类型、PCB叠层信息和相关芯片型号、位号，即可由程序调用预先配置的芯片数据库，自动完成导入PCB设计文件、设置叠层、生成端口、剪裁PCB、配置仿真参数、运行仿真、处理S参数、生成报告的步骤，使仿真工程师能从机械重复的软件操作中解放出来，专注于分析SI/PI问题和提出优化方案，有效提高互连设计验证、优化迭代效率，帮助加快项目研发进度。
Xiangcheng Li
UNISOC
08/19/2025 13:00
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In the recent years, there has been significant growth in semiconductor design activity and forecasts indicate this trend to only increase in the future. RTL design and verification are key challenges in the semiconductor design cycle and acceleration via emulation has been predominant in the industry for decades, however, the adoption of this technology has primarily catered to the needs of large-scale ‘billion-gate’ class designs in recent years.
There are design teams that create IP or small-scale yet mission critical ASIC/SoC designs across organizations that strive to enable emulation to accelerate their D&V process but existing enterprise-based emulators in the industry are typically out of reach for these users due to a variety of reasons such as limited capital budget, low priority in resource allocation, or small companies that lack the data center infrastructure to house these large-scale emulators.
To reduce the barrier of adoption, Cadence is introducing a solution to address this market demand – Palladium Z3 System Studio. It is a stand-alone emulation appliance tailored for emulating designs of up to 128 million gates. In this session, we intend to present the benefits and solutions of Palladium Z3 System Studio, a leading-edge emulation appliance lowering the adoption barrier significantly for D&V teams to accelerate their hardware/software co-verification workloads.
Michael Young
Cadence
08/19/2025 13:30
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Jin Yuan
GravityXR
08/19/2025 14:00
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功耗对于AI芯片的重要性不言而喻，尤其在AI产品日新月异的今天，其优化与控制直接关系到产品的性能表现、续航能力乃至市场竞争力。在实际项目运作中，功耗问题已成为衡量产品成败的关键标尺。一个卓越的功耗管理策略不仅能提升能效比、缩减运营成本，还能增强系统稳定性与可靠性，从而延长产品使用寿命。
然而，当前的功耗分析流程却面临重重挑战。随着芯片规模的不断膨胀和内部接口的日益复杂化，传统功耗分析方法显得捉襟见肘，难以做到系统级的功耗计算，导致分析结果存在局限性。此外，芯片在实际应用中的场景复杂多变且持续时间较长，但受限于现有工具，功耗分析往往只能针对片段进行，这种碎片化的分析方式不仅无法准确反映芯片在真实场景下的全流程功耗状况，还可能遗漏关键功耗问题。更为棘手的是，片段的选择往往基于经验而非数据支持，这无疑降低了分析结果的可信度。
在芯片设计的早期功耗探索阶段和后期的快速功耗评估阶段，我们也缺乏足够的手段来支撑，导致无法及时发现并解决潜在的功耗问题，也无法在后期阶段迅速进行优化。同时，功耗分析报告的生成涉及跨部门、跨工具的协作，这不仅增加了工作流程的复杂性，还延长了报告生成的周期。
针对上述功耗分析流程的瓶颈与不足，Cadence推出了基于Palladium硬件仿真加速平台的动态功耗分析（DPA）解决方案。该方案能够对运行复杂真实测试用例的全芯片大规模设计进行全方位的功耗评估与分析，提供峰值功耗区间识别、高活跃模块指出、IR Drop预警以及功耗变化趋势展示等多维度功耗数据。
DPA流程以其高效性、准确性和灵活性著称。首先，依托Palladium硬件仿真加速平台，DPA能够迅速完成功耗分析，显著提升分析效率。其次，DPA能够精确读取Liberty文件和Spef文件中的功耗信息，并结合Palladium网表环境进行更为精准的功耗分析，确保分析结果的可靠性。最后，DPA支持多种测试场景和灵活的分析方式，能够满足不同项目阶段和不同分析需求。在实际项目中，DPA的介入使得项目团队能够在早期RTL阶段就对功耗情况进行初步估算和分析，及时发现并解决潜在的功耗问题。在项目中后期，DPA能够对重点模块进行多样、灵活且快速精准的功耗分析，为项目的顺利推进提供有力保障。
综上所述，基于Palladium硬件仿真加速器的动态功耗分析（DPA）解决方案成功破解了当前功耗分析流程的难题，显著提升了功耗分析的效率和准确性。该方案为打造卓越的AI芯片产品提供了坚实可靠的功耗管理支撑，为项目的成功实施奠定了坚实基础。
Kai Xing
KUNLUNXIN
08/19/2025 14:30
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随着人工智能（AI）和高性能计算领域的爆发式成长，“多芯片集成”（Multi-Die）架构正成为解决日益增长的计算需求的关键策略。在这一背景下，“多芯片集成”不仅能够应对复杂的系统挑战和繁重的工作负载难题，在芯片设计与开发过程中，IC验证在检测设计缺陷、保障项目进度方面发挥着至关重要的作用。然而，“多芯片集成”系统的引入带来了新的考验：由于其结构复杂且规模庞大，IC验证的工作量显著增加至以往难以想象的程度——单次全面运行已成为不可能完成的任务。因此IC验证亦需要革新与升级。针对这种Multi-Die架构的传统验证方式，是将系统级“仿真”任务分解为多个子系统级环境并行执行，尽管这一方法解决了仿真时间长的问题，但缺乏整个系统级仿真导致的潜在故障泄露的风险不容忽视。在此背景下，Cadence 功能验证解决方案凭借“分布式仿真”技术为这一难题提供了解决方案。它允许将大规模的“仿真”作业分解至分布式计算环境中执行，能够实现多个可执行文件之间的高效协作——即每个“simv实例”都能独立运行或与其他实例并行交互，从而提升了整体性能表现。相较于传统意义上的单一可执行模式而言，“分布式仿真的优势在于其灵活度高、扩展性强。”这意味着无论面临何种规模或复杂度的任务场景时都能够快速响应并做出相应调整；同时由于减少了对大型主机及集群计算机资源的需求量进而有效控制了总体运营成本。因此面对不断演进的技术环境与愈发严峻的竞争态势，使用诸如“分布式仿真”在内的先进验证技术变得至关重要。本文主要介绍cadence分布式仿真技术的使用流程，并给出了使用该技术对大规模Multi-Die系统仿真的助力探索，以及对未来应用前景的展望。
Jiashan Xu
Sanechips
08/19/2025 15:00
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随着集成电路技术的飞速发展，应用处理器（AP）芯片在性能和功耗方面的平衡成为设计的关键挑战。本文聚焦于基于Palladium平台的AP芯片性能功耗验证，探讨了如何利用Palladium平台的高性能仿真能力，实现对AP芯片在复杂应用场景下的性能和功耗特性进行全面验证。首先，介绍了Palladium平台的架构优势，包括其在硬件加速仿真和快速原型验证方面的独特能力。其次，详细阐述了验证流程，包括建立验证环境、设计测试用例以及开发功耗评估模型。通过与传统仿真方法的对比，展示了Palladium平台在验证效率和准确性上的显著提升。实验结果表明，该平台能够在较短时间内完成大规模AP芯片的性能和功耗验证，为芯片设计优化提供了有力支持。本文的研究为AP芯片的高效验证提供了新的思路和方法，有助于缩短芯片开发周期并降低设计风险。
Yuxuan Zhen
Xiaomi
08/19/2025 15:30
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08/19/2025 16:00
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在先进工艺节点的复杂Soc验证中，门级仿真面临三重技术挑战：
其一，规模膨胀效应导致仿真速度呈超线性下降，十亿级晶体管设计单次仿真周期可达数百小时；
其二，时序反标复杂性，传统的SDF反标过程需要解析多层次的互连延迟（Hierarchical Interconnect Delay），这在大型网表中会导致额外的编译和仿真的时间消耗；
其三，信号访问效率瓶颈，全芯片信号探针的接入不仅增加了内存占用量，还带来了额外的编译时间成本。
本文提出基于Cadence Xcelium工具的协同优化方法，通过关闭非关键计算与精细化信号访问控制，实现仿真性能的显著提升。针对传统层次化互连延迟计算（ACG）在零延迟SDF（Zero-Delay SDF）和伪时序SDF（fake SDF）场景下的冗余开销，本研究创新性地采用 -NOACG 编译选项，规避Annotated Connection Graph的层次化互连延迟迭代计算，在门级仿真前期验证环境准备阶段对时序缺陷率无要求的场景中减少编译仿真耗时，提升4x以上的加速验证迭代。其次，开发动态访问控制引擎，采用语法树驱动型afile生成算法（Genafile Automation），将信号访问范围从全芯片收敛至全芯片1%的关键路径模块，结合 -access +r 最小权限策略，实现3x以上的增量编译加速与至少30%的存储占用削减。本方案已成功部署于复杂Soc芯片项目，为高复杂度、低功耗芯片门级验证提供可扩展的加速范式。
Yang Lin
UNISOC
08/19/2025 16:30
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将vManager嵌入inhouse工具，协助将验证签核从CDV过渡到MDV，实现更高效地验证迭代与回归管理。对回归状态与进度、fail分类与趋势等，进行可视化地查看与跟踪。
1. 通过嵌入inhouse工具，保持入口不变，以低用户感知度的方式，平滑切换到mdv flow。一键生成vsif文件，并执行回归。适配已有的error_filter文件，对回归结果进一步检查。将coverage、回归结果反标到spec，在coverage百分比之外，以vplan完备度和反标率，更好地完成质量跟踪。
2. 优化rerun流程，选择dump的不同格式的波形，适配不同场景对波形的要求。
3. 回归结束后，inhouse工具备份db，清除仿真过程中的log等文件，减少对磁盘空间的占用。
4. tracking界面的可视化图表，查看验证进度、cov收敛趋势、passrate趋势、人力投入等，提高验证管理效率。
5. 结合AI APP，缩短问题定位耗时，优化回归随机空间，提高问题定位和回归效率。
本方案为如何借助vmanager平滑切换至mdv flow提供了参考，为验证进度和质量评估提供可视化方案，为实现AI加速验证迭代、提升效率，提供了思路。
Jiangheng Pei
UNISOC
08/19/2025 17:00
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当前基于算法生成测试向量（TV）的直接验证方法存在两大关键性瓶颈，影响开发周期
1、用例冗余率高：同类数据批量生成的测试场景重合度显著，产生40%以上冗余用例
2、迭代成本高：算法平台任何改动均需全量重新生成用例，导致验证周期延长30%-50%
本文提出了一种基于Cadence IMC Rank工具的覆盖率动态分析方法，通过构建多维度覆盖率模型（包括功能覆盖率、代码覆盖率与断言覆盖率），结合工具自动化筛选机制实现了验证用例的优先级排序。实验结果表明，本研究提出的方法在实际验证项目中展现出显著效能提升和精准优化。测试用例池的有效率达100%，冗余用例消除率超90%，回归测试周期缩短至传统方法的1/24，有效解决了IP验证过程中测试冗余度大、收敛周期长等关键问题，为复杂芯片功能验证提供了高效的解决方案框架。
Peiqian Chen
UNISOC
08/19/2025 13:00
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Since the emergence of Artificial Intelligence (AI), it has had a profound impact across various fields, transforming the way we live and work. Whether in healthcare, transportation, education, finance, or other sectors, AI continues to evolve and develop, bringing significant changes to human life.
With the rapid growth of smart devices, semiconductor chips are being applied in an increasing number of markets, and EDA (Electronic Design Automation) is undergoing a revolution. Driven by market demand, process advancements, and tighter industry chain integration, chip complexity continues to rise. As we move from chip-level to system-level design, traditional design concepts and methods are clearly no longer sufficient.
Against this backdrop, Cadence has taken the lead in launching the industry's first full-stack AI solution from chip to system level—Cadence.AI. This includes Cadence’s Verisium Verification platform. The Verisium Verification platform empowers the verification for ultra-large-scale chips and systems greatly enhancing the productivity for verification and helping users achieve sustained success in the new era of AI.
Rich Chang
Cadence
08/19/2025 13:30
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随着产品需求日益复杂导致芯片设计规模逐步增大，芯片验证面临随机化场景复杂多样，
测试用例数量庞大的情况，随之带来仿真回归时间久，覆盖率收敛困难等问题，并且芯片开发过
程中产品需求可能变更，导致验证周期压缩，从而对验证快速回归和收敛提出更高的要求。本文
基于Cadence 推出的SIM AI 技术以及vManager 工具和Jenkins 持续集成，提出了一种新的自动
化仿真回归方法，利用SIM AI 工具学习产生新的vSif 文件，通过vManager 和Jenkins 实现自动
化仿真迭代。对比了相同验证环境下应用SIM AI 前后在回归时间、缺陷复现、覆盖率收敛效果
的差异，仿真数据表明SIM AI 在用例随机化较好的情况下，可以大幅压缩回归时间，协助缺陷
挖掘，加速覆盖率收敛。同时在回归过程中，发挥了vManager 和Jenkins 自动化部署仿真的优
势，简化验证工程师操作流程，最终实现芯片验证仿真回归的快速迭代，有效提升验证交付效率。
Feng Tian & Haohao Sun
Sanechips
08/19/2025 14:00
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MDV (Metric-Driven Verification) is a well-established methodology for verifying the functionality of a DUT (Design Under Test). AIGC (Artificial Intelligence Generated Content) has emerged as a transformative technology that enhances engineering workflows and improves verification efficiency. Verisium, a comprehensive verification platform developed by Cadence, integrates MDV with AIGC through its suite of tools: Verisium Manager, Verisium Debug, and Verisium AI Apps. This integration forms a new verification paradigm, the MDAI (Manager-Debugger-AI Helper) workflow, which has been applied to two projects, demonstrating up to a 5x improvement in efficiency.
Verisium provides an ecosystem in which:
The Manager monitors verification metrics, including pass/fail rates and coverage analysis.
The Debugger facilitates debugging through code inspection, schematic analysis, and waveform visualization.
The AI Helper enhances efficiency, productivity, and proficiency through automation and AI-driven insights.
This paper is structured into three sections, each detailing a key component of the MDAI workflow:
Verisium AI Apps – An evaluation of CodeMiner, WaveMiner, and AutoTriage is discussed in this part including their applications to two projects. The efficiency of AI-assisted debugging is compared against manual debugging, demonstrating improvements ranging from ~2x to ~5x depending on the scenario. CodeMiner is an advanced design verification debug tool to report the semantic differences between two simulations. WaveMiner is an advanced multi-run waveform analysis App that minimizes the debugging effort by automating the root cause analysis of misbehavior introduced between two versions of the same RTL design. AutoTriage is a powerful tool that utilizes machine learning algorithms to group failed test runs based on similar reasons, creating proposed failure clusters from historical data or new failed runs.
Verisium Debug – A comparative analysis of SimVision and Verisium Debug, highlighting key features such as VWDB (Cadence’s next-generation Waveform Dump Database), FRD (Force Release Deposit), and LP (Low Power). Additionally, challenges in adoption and FAQ (frequently asked questions) are discussed.
Verisium Manager – An exploration of its role within the MDAI workflow, including its distinction from IMC (Integrated Metric Center) and its function in managing verification projects across multiple sites.
In conclusion, this paper presents an overvi
Shawn Zhang
Analog Devices
08/19/2025 14:30
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在复杂以太交换芯片设计的验证流程中，调试效率直接影响项目进度。Cadence 的 Verisium Debug 作为调试工具，被广泛应用于软仿真（Xcelium）和硬仿真（Palladium）环境，以提升问题定位的效率。本文结合 中兴微电子 在实际工程中的使用经验，探讨 Verisium Debug 在软仿（软件仿真）和硬仿（硬件加速仿真）中的应用优势，同时分析其与 vManager 和 SmartRun 在回归测试中的配合效果。
Sihang Shang
Sanechips
08/19/2025 15:00
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随着以太网芯片设计复杂度的日益提升，以太芯片接口模块在整体架构中的占比显著增加，其中包接口模块作为关键组成部分，其功能正确性对芯片性能至关重要。形式化验证(Formal Property Verification, FPV)凭借其全状态空间遍历的独特优势，能够无遗漏地验证设计的所有可能状态，在包接口模块的验证中展现出显著的技术优势。但不可忽视的是，包接口模块的输入输出通常不具备端到端的特性，且接口组合复杂多样，这些因素极大地增加了断言(SVA，SystemVerilog Assertions)编写的复杂性。而高质量的SVA编写对验证人员的能力有着较高要求，其开发成本往往占据了总体验证成本的50%以上。因此，如何降低SVA编写成本、提升断言开发效率，已成为包接口模块形式化验证中急待解决的关键问题。针对上述挑战，本文提出了一种针对包接口模块端到端的形式化解决方案：FPVIP(Formal Pkt Verification Intellectual Property)。FPVIP将形式化验证方法论进行封装，提供了更高层次的抽象接口，降低了SVA编写的难度与成本的同时，保持了形式化验证的完备性优势。该解决方案由两部分构成：Formal Seq VIP和Formal Func VIP。Formal Seq VIP能够灵活控制发包时间、包类型、包长度等关键信息，实现端到端的验证，进而简化了断言编写和问题定位的流程。而Formal Func VIP则专注于包接口模块的通用功能，提供了一套完整且经过严格验证的形式化断言库，配合Formal Seq VIP可显著提升验证效率。FPVIP目前已成功应用于中兴微电子的交换芯片项目中。实验结果表明，4名无Formal验证经验的开发人员仅需接受3小时的SVA语法与FPVIP使用培训，便可在7天内完成其开发模块的形式化验证工作。与传统Formal验证方法相比，使用FPVIP将验证时间缩短了50%，并成功发现了28个潜在的设计缺陷。这一成果充分证明了FPVIP在降低验证门槛、提升验证效率以及提高缺陷检出率方面的显著优势。
Sihang Shang
Sanechips
08/19/2025 15:30
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08/19/2025 16:00
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JasperGold Connectivity Verification 是Cadence开发的一种专门验证连接性的形式验证工具，采用数学分析的方式,无需灌输激励,工具会自动遍历穷举，可以有效提高PINMUX以及其他规律性硬件设计的验证完备性。
1. 使用python脚本自动生成Formal工具所需要的csv文件，对于SOC级验证，Jasper CONN工具有反向抽取CSV的命令，有效解决了传统繁琐重复的工作;
2. 可以将formal产生的coverage db文件和simulation验证收集的cov进行merge，加速signoff收敛;
3. Formal验证环境仅需一小时即可搭建完成。Formal验证将原来UVM环境搭建所需的10,000多行代码精简到仅 588行。从单轮PINMUX验证时间来看，Formal验证一小时即可完成。在最后的signoff中，Formal验证仅需三天，效率提高了约4.67 倍:
本方案为连接性验证提供了参考并有实践数据支撑，该方案终结了传统验证方案的痛点，环境搭建更简单，不需要输入复杂激励，且支持和simulation coverage 做merge处理；对业内同类业务场景具备较好的通用性和应用借鉴;
Chengzhe Li
UNISOC
08/19/2025 16:30
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在现代大规模AI硬件加速器的设计中，无论是选择DSA还是GPGPU的架构，都需要保持对于AI算法创新和应用场景的高度敏感和关注，这是因为AI硬件加速器的设计与AI算法的发展相辅相成。随着深度学习、神经网络算法的不断演进，其对大规模矩阵运算、卷积计算等复杂计算任务提出了更高的性能、能效和实时性要求，促使硬件设计者需要不断优化芯片的设计架构，以适应诸如GPT/Gemini/ERNIE等大模型的云端和本地部署需求。
然而在当前半导体制造工艺进步受限的情况下，芯片面积无法随需求等比例增加，前端设计团队不仅要应对功能不断扩展、时序要求不断严格的挑战，还需要在激烈的市场竞争中尽快将产品推向流片量产。传统的验证流程已无法满足设计迭代与精度收敛的要求。在这样的背景下，Cadence推出的C2RTL工具应运而生，通过形式化验证加速，为设计工程师提供了一条从高层次算法到低层次实现的高效通路，极大缩短了设计周期并显著提高了验证效率。
飞速发展的AI算法给各家AI芯片中Datapath设计提出了更加苛刻的要求，纷繁复杂的数据类型和运算类型在排列组合的作用下输出了愈发膨胀的指令数量，一方面Datapath设计需要在支持的指令数量暴增的情况下，保证面积和时序的稳定。另一方面设计迭代的时间被竞争激烈的市场压缩。如果没有强力验证工具的支持，很难在保证计算精度符合要求的情况下，进行PPA上的迭代优化。例如，最近Microsoft联合推广的Microscaling技术，就需要最新的AI加速器支持诸如FP8/FP6/FP4等不在IEEE 754标准下的新浮点类型。在进行低精度推理的场景下，对于这些新的数据类型有更高的算力需求，同时又需要保证计算精度在规定的误差内。
传统仿真验证方法包括RIG（Random Instruction Generator）随机生成计算指令流加上定向的浮点测试集作为激励，配合日常的regression list打造专属case进行定向遍历，争取在特定时间范围内覆盖绝大多数计算指令和浮点计算下的corner 场景。这种传统仿真验证依赖大量测试向量，但仍难以覆盖100%的边界条件和极限情况，容易留下潜在隐患。过了特定开发节点后难以进行ECO，且软件解决方案也难以绕过特定输入下的错误输出。而前端设计人员同样需要在保证计算精度和功能正确性的情况下，进行高层次算法模型和RTL上的设计空间探索，前期基于时序和面积综合考虑而确定的更优解方案如果在长期的回归验证中才暴露出问题，往往不会有更多时间留给前端设计人员重新调整优化方案，从而影响项目的整体推进进度。因此，如何实现从算法到RTL代码的自动化转换，同时在转换过程中嵌入高效的形式化验证机制，成为AI芯片设计领域亟待解决的核心问题。
在我司（昆仑芯）的使用案例中，有两点体现了Cadence Jasper C2RTL的价值。其一是在浮点datapath重构时期，加速了FMAC的精度收敛，当下的AI芯片架构中，往往要求FMAC单元支持多种数据类型的并行计算和输出。并且特定应用场景下对不同数据类型的并行算力需求也各不相同，例如对于FP32这种高精度计算的并行度会比FP16/BF16/TF32以及FP8/FP6/FP4这些低精度计算要低。如果在单个计算单元内对不同并行度要求的数据类型的datapath做融合提升面积效率，逻辑复杂度会大幅提高，需要C2RTL Formal工具协助进行快速的RTL功能debug，同时尝试不同类型的融合方案，找到PPA上的最优解。对于低精度的浮点类型，可以尝试直接证明，而对于高精度的浮点类型如FP32/FP64，通过使用优化后的proof structure进行计算空间的拆分，以及proofgrid机制利用lsf集群并行加速证明过程的收敛。
其二是对于新的数据类型计算，在FP8/FP6/FP4等类型的加入下，软件侧功能模拟器同样需要独立开发全新的c model，以支持前仿阶段的功能验证。在以往如果仅仅是前端设计人员与功能模拟器人员手动对齐算法实现细节，往往存在引导者对被引导者的关系，这会导致引导者self-proof的情况出现。而现在双方对齐后的实现细节可以通过c model先行的方式利用C2RTL进行私有c model实现与开源库接口实现进行对比的方式优先校准功能模拟器，之后保持功能模拟器稳定进行大范围的前仿回归验证。快速实现c model对齐→ RTL对齐的两个阶段。
Bowen Li & Hexin Bao
KUNLUNXIN
08/19/2025 17:00
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Chiplets enable considerable gains in agility, scaling, and TTM. To unleash the full potential of this promise, it is required that the various chiplets be trusted in terms of provenance. An incorrect mix and match of inconsistent or even rogue chiplets would undermine the viability of the approach. Hence caring about cybersecurity is a prerequisite.
In this presentation, we adopt an analytical posture to address the question of System-in-Package (SiP) trustworthiness. We show that existing cybersecurity functions can be leveraged to emerge secure chiplets aggregation. We also demonstrate that the solution can be implemented as part of a reference chiplet architecture, as provided by Cadence Silicon Solution Group (SSG) / Compute Solutions Group (CSG).
The SiP will be trusted if two properties are safeguarded: Hardware & Software Bill of Material (HBOM and SBOM) secure provenance and integrity.
In a risk analysis approach, we MUST consider threat agents. Their exact nature and intentions are hard to predict exhaustively, but let us give some examples:
- Nation states attacks exploiting the supply chain;
- Incorrect HBOM or SBOM leading to configuration errors thereby voiding safety guarantees;
- Economic fraud abusing the chiplet business model, through supply of lower PPA chiplets or overbuilding.
For those reasons, security is a system-level overarching requirement.
It is mostly a cybersecurity (security orchestrated at logic level) topic, which nonetheless should be reinforced by a physical security dimension as attackers can procure chiplets from the open market to train their attacks (reconnaissance phase).
Cadence partners with Secure-IC to offer to their Customers the best-of-breed security solution, which has been proven suitable for chiplets.
It is backed on multicertified IPs and vetted cybersecurity concepts:
- security by default, hence end-to-end security, from pre-silicon to mission mode, incl. through delegation
- fail secure, i.e., whatever happens, the S500 solution does not compromise the security
- resiliency: the system does not brick in case of an issue (bug or attack), but leave it possible for the user to recover through diagnose services
- minimality of the design, to allow for agnosticity wrt use-cases
- defense in depth (e.g., software no touch key, or Internal Key Generation)
- capability to debug securely
- capability to manage (multi-domain) power securely
- pre-compliance by activating configuration items
Sylvain GUILLEY
Secure-IC